Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
| Date         : Thu Jun  8 10:54:21 2023
| Host         : DESKTOP-5QEHRRG running 64-bit major release  (build 9200)
| Command      : report_methodology -file basys3top_methodology_drc_routed.rpt -pb basys3top_methodology_drc_routed.pb -rpx basys3top_methodology_drc_routed.rpx
| Design       : basys3top
| Device       : xc7a35tcpg236-1
| Speed File   : -1
| Design State : Fully Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 12
+-----------+----------+-------------------------------+------------+
| Rule      | Severity | Description                   | Violations |
+-----------+----------+-------------------------------+------------+
| TIMING-18 | Warning  | Missing input or output delay | 12         |
+-----------+----------+-------------------------------+------------+

2. REPORT DETAILS
-----------------
TIMING-18#1 Warning
Missing input or output delay  
An output delay is missing on seg[0] relative to the rising and/or falling clock edge(s) of clk.
Related violations: <none>

TIMING-18#2 Warning
Missing input or output delay  
An output delay is missing on seg[1] relative to the rising and/or falling clock edge(s) of clk.
Related violations: <none>

TIMING-18#3 Warning
Missing input or output delay  
An output delay is missing on seg[2] relative to the rising and/or falling clock edge(s) of clk.
Related violations: <none>

TIMING-18#4 Warning
Missing input or output delay  
An output delay is missing on seg[3] relative to the rising and/or falling clock edge(s) of clk.
Related violations: <none>

TIMING-18#5 Warning
Missing input or output delay  
An output delay is missing on seg[4] relative to the rising and/or falling clock edge(s) of clk.
Related violations: <none>

TIMING-18#6 Warning
Missing input or output delay  
An output delay is missing on seg[5] relative to the rising and/or falling clock edge(s) of clk.
Related violations: <none>

TIMING-18#7 Warning
Missing input or output delay  
An output delay is missing on seg[6] relative to the rising and/or falling clock edge(s) of clk.
Related violations: <none>

TIMING-18#8 Warning
Missing input or output delay  
An output delay is missing on seg[7] relative to the rising and/or falling clock edge(s) of clk.
Related violations: <none>

TIMING-18#9 Warning
Missing input or output delay  
An output delay is missing on ssel[0] relative to the rising and/or falling clock edge(s) of clk.
Related violations: <none>

TIMING-18#10 Warning
Missing input or output delay  
An output delay is missing on ssel[1] relative to the rising and/or falling clock edge(s) of clk.
Related violations: <none>

TIMING-18#11 Warning
Missing input or output delay  
An output delay is missing on ssel[2] relative to the rising and/or falling clock edge(s) of clk.
Related violations: <none>

TIMING-18#12 Warning
Missing input or output delay  
An output delay is missing on ssel[3] relative to the rising and/or falling clock edge(s) of clk.
Related violations: <none>


